1. Field of the Invention
The invention relates to a fabrication method for memory devices, and more particularly to a method for fabricating a bit line contact of a memory device.
2. Description of the Related Art
Currently, the bit line contact is fabricated by a self-aligned process during the fabrication of a dynamic random access memory (DRAM). At first, the insulating layer and the sacrificial layer are formed on the substrate, followed by patterning by a photolithography/etching process to define the area where the bit line contact is to be later formed. Next, the sacrificial layer and the insulating layer are removed, and the contact hole is formed. The metal plug is then filled in the contact hole to complete fabrication of the bit line contact.
FIG. 1 is a cross section of an unfinished memory device fabricated by a conventional method. Referring to FIG. 1, the gate electrode stacks 2 are formed on the substrate 1, and therebetween, the doped region 3 is formed in the substrate 1. In FIG. 1, the boron phosphate silicon glass (BPSG) layer 4 is formed over the substrate 1, followed by removal of the polysilicon sacrificial layer 5 to form the contact hole 7. When the sacrificial layer 5 is being removed, the etching rate of the polysilicon sacrificial layer of the peripheral substrate is smaller than the etching rate of the polysilicon sacrificial layer of the central substrate. As a result, the polysilicon sacrificial layer 5 of the peripheral substrate remains at the bottom of the contact hole 7. Since the polysilicon sacrificial layer 5 remains at the bottom of the contact hole 7, the silicon oxide layer 6 at the bottom of the contact hole 7 can not be completely removed. Accordingly, the metal plug later formed can not be completely in contact with the doped region 3, resulting in bit line contact failure.
Thus, a fabrication method for memory devices eliminating the described problems is required.